The method of mapping the consecutive memory blocks to consecutive cache blocks is called

  • Direct Mapping – The simplest technique, known as direct mapping, maps each block of main memory into only one possible cache line. or

    In Direct mapping, assign each memory block to a specific line in the cache. If a line is previously taken up by a memory block when a new block needs to be loaded, the old block is trashed. An address space is split into two parts index field and a tag field. The cache is used to store the tag field whereas the rest is stored in the main memory. Direct mapping`s performance is directly proportional to the Hit ratio.

    i = j modulo m where i=cache line number j= main memory block number m=number of lines in the cache

    For purposes of cache access, each main memory address can be viewed as consisting of three fields. The least significant w bits identify a unique word or byte within a block of main memory. In most contemporary machines, the address is at the byte level. The remaining s bits specify one of the 2s blocks of main memory. The cache logic interprets these s bits as a tag of s-r bits (most significant portion) and a line field of r bits. This latter field identifies one of the m=2r lines of the cache.

  • Associative Mapping –
    In this type of mapping, the associative memory is used to store content and addresses of the memory word. Any block can go into any line of the cache. This means that the word id bits are used to identify which word in the block is needed, but the tag becomes all of the remaining bits. This enables the placement of any word at any place in the cache memory. It is considered to be the fastest and the most flexible mapping form.
  • Set-associative Mapping –
    This form of mapping is an enhanced form of direct mapping where the drawbacks of direct mapping are removed. Set associative addresses the problem of possible thrashing in the direct mapping method. It does this by saying that instead of having exactly one line that a block can map to in the cache, we will group a few lines together creating a set. Then a block in memory can map to any one of the lines of a specific set..Set-associative mapping allows that each word that is present in the cache can have two or more words in the main memory for the same index address. Set associative cache mapping combines the best of direct and associative cache mapping techniques.

    In this case, the cache consists of a number of sets, each of which consists of a number of lines. The relationships are

    m = v * k i= j mod v where i=cache set number j=main memory block number v=number of sets m=number of lines in the cache number of sets k=number of lines in each set

    Application of Cache Memory –

    1. Usually, the cache memory can store a reasonable number of blocks at any given time, but this number is small compared to the total number of blocks in the main memory.
    2. The correspondence between the main memory blocks and those in the cache is specified by a mapping function.


    Types of Cache –

    • Primary Cache –
      A primary cache is always located on the processor chip. This cache is small and its access time is comparable to that of processor registers.
    • Secondary Cache –
      Secondary cache is placed between the primary cache and the rest of the memory. It is referred to as the level 2 (L2) cache. Often, the Level 2 cache is also housed on the processor chip.


    Locality of reference –
    Since size of cache memory is less as compared to main memory. So to check which part of main memory should be given priority and loaded in cache is decided based on locality of reference.

    Types of Locality of reference

    1. Spatial Locality of reference
      This says that there is a chance that element will be present in the close proximity to the reference point and next time if again searched then more close proximity to the point of reference.
    2. Temporal Locality of reference
      In this Least recently used algorithm will be used. Whenever there is page fault occurs within a word will not only load word in main memory but complete page fault will be loaded because spatial locality of reference rule says that if you are referring any word next word will be referred in its register that’s why we load complete page table so the complete block will be loaded.

    GATE Practice Questions –

    Que-1: A computer has a 256 KByte, 4-way set associative, write back data cache with the block size of 32 Bytes. The processor sends 32-bit addresses to the cache controller. Each cache tag directory entry contains, in addition, to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The number of bits in the tag field of an address is

    (A) 11 (B) 14 (C) 16 (D) 27

    Answer: (C)

    Explanation: https://www.geeksforgeeks.org/gate-gate-cs-2012-question-54/amp/

    Que-2: Consider the data given in previous question. The size of the cache tag directory is

    (A) 160 Kbits (B) 136 bits (C) 40 Kbits (D) 32 bits

    Answer: (A)

    Explanation: https://www.geeksforgeeks.org/gate-gate-cs-2012-question-55/amp/

    Que-3: An 8KB direct-mapped write-back cache is organized as multiple blocks, each of size 32-bytes. The processor generates 32-bit addresses. The cache controller maintains the tag information for each cache block comprising of the following.

    1 Valid bit 1 Modified bit

    As many bits as the minimum needed to identify the memory block mapped in the cache. What is the total size of memory needed at the cache controller to store meta-data (tags) for the cache?

    (A) 4864 bits (B) 6144 bits (C) 6656 bits (D) 5376 bits

    Answer: (D)

    Explanation: https://www.geeksforgeeks.org/gate-gate-cs-2011-question-43/amp/

    Article Contributed by Pooja Taneja and Vaishali Bhatia. Please write comments if you find anything incorrect, or you want to share more information about the topic discussed above.


  • Please log in or register to add a comment.

    Please log in or register to answer this question.

    Please log in or register to add a comment.

    This set of Computer Organization and Architecture Multiple Choice Questions & Answers (MCQs) focuses on “Mapping Functions”.

    1. The memory blocks are mapped on to the cache with the help of ______ a) Hash functions b) Vectors c) Mapping functions d) None of the mentioned

    View Answer

    Answer: c
    Explanation: The mapping functions are used to map the memory blocks on to their corresponding cache block.

    2. During a write operation if the required block is not present in the cache then ______ occurs. a) Write latency b) Write hit c) Write delay d) Write miss

    View Answer

    Answer: d
    Explanation: This indicates that the operation has missed and it brings the required block into the cache.

    3. In ________ protocol the information is directly written into the main memory. a) Write through b) Write back c) Write first d) None of the mentioned

    View Answer

    Answer: a
    Explanation: In case of the miss, then the data gets written directly in main memory.

    Note: Join free Sanfoundry classes at Telegram or Youtube

    4. The only draw back of using the early start protocol is _______ a) Time delay b) Complexity of circuit c) Latency d) High miss rate

    View Answer

    Answer: b
    Explanation: In this protocol, the required block is read and directly sent to the processor.

    5. The method of mapping the consecutive memory blocks to consecutive cache blocks is called ______ a) Set associative b) Associative c) Direct d) Indirect

    View Answer

    Answer: c
    Explanation: This method is most simple to implement as it involves direct mapping of memory blocks.

    6. While using the direct mapping technique, in a 16 bit system the higher order 5 bits are used for ________ a) Tag b) Block c) Word d) Id

    View Answer

    Answer: a
    Explanation: The tag is used to identify the block mapped onto one particular cache block.

    7. In direct mapping the presence of the block in memory is checked with the help of block field. a) True b) False

    View Answer

    Answer: b
    Explanation: The tag field is used to check the presence of a mem block.

    8. In associative mapping, in a 16 bit system the tag field has ______ bits. a) 12 b) 8 c) 9 d) 10

    View Answer

    Answer: a
    Explanation: The Tag field is used as an id for the different memory blocks mapped to the cache.

    9. The associative mapping is costlier than direct mapping. a) True b) False

    View Answer

    Answer: a
    Explanation: In associative mapping, all the tags have to be searched to find the block.

    10. The technique of searching for a block by going through all the tags is ______ a) Linear search b) Binary search c) Associative search d) None of the mentioned

    View Answer

    Answer: c
    Explanation: None.

    11. The set-associative map technique is a combination of the direct and associative technique. a) True b) False

    View Answer

    Answer: a
    Explanation: The combination of the efficiency of the associative method and the cheapness of the direct mapping, we get the set-associative mapping.

    12. In set-associative technique, the blocks are grouped into ______ sets. a) 4 b) 8 c) 12 d) 6

    View Answer

    Answer: d
    Explanation: The set-associative technique groups the blocks into different sets.

    13. A control bit called _________ has to be provided to each block in set-associative. a) Idol bit b) Valid bit c) Reference bit d) All of the mentioned

    View Answer

    Answer: b
    Explanation: The valid bit is used to indicate that the block holds valid information.

    14. The bit used to indicate whether the block was recently used or not is _______ a) Idol bit b) Control bit c) Reference bit d) Dirty bit

    View Answer

    Answer: d
    Explanation: The dirty bit is used to show that the block was recently modified and for a replacement algorithm.

    15. Data which is not up-to date is called as _______ a) Spoilt data b) Stale data c) Dirty data d) None of the mentioned

    View Answer

    Answer: b
    Explanation: None.

    Sanfoundry Global Education & Learning Series – Computer Organisation and Architecture.

    • Get Free Certificate of Merit in Computer Organization and Architecture
    • Participate in Computer Organization and Architecture Certification Contest
    • Become a Top Ranker in Computer Organization and Architecture
    • Take Computer Organization and Architecture Tests
    • Chapterwise Practice Tests: Chapter 1, 2, 3, 4, 5, 6, 7, 8, 9, 10
    • Chapterwise Mock Tests: Chapter 1, 2, 3, 4, 5, 6, 7, 8, 9, 10

    The method of mapping the consecutive memory blocks to consecutive cache blocks is called

    Manish Bhojasia, a technology veteran with 20+ years @ Cisco & Wipro, is Founder and CTO at Sanfoundry. He lives in Bangalore, and focuses on development of Linux Kernel, SAN Technologies, Advanced C, Data Structures & Alogrithms. Stay connected with him at LinkedIn.

    Subscribe to his free Masterclasses at Youtube & technical discussions at Telegram SanfoundryClasses.